Advanced focal plane arrays (FPAs), such as infrared focal plane arrays (IRFPAs) utilize embedded analog-to-digital converters (ADCs) on the read out integrated circuitry (ROIC) die to enable on-chip digital signal processing, increased dynamic range, and increased signal to noise ratio. On-ROIC ADC is often incorporated at one or more FPA outputs or at ROIC columns. More ADCs on the ROIC tend to provide increased digital resolution and reduced ADC power due to reduced digitization frequency.
A digital pixel sensor (DPS) utilizes one on-ROIC ADC per pixel to take advantage of the benefits of on-chip digital processing. Specifically, in-pixel digital readouts enable an increase in the well depth of sensors while avoiding large integration capacitors. However, to avoid high quantization noise, some readouts are implementing split bits where the M most significant come from an in-pixel digital counter, and the N least significant come from a conventional analog-to-digital convertor that digitizes residual charge on the integration capacitor at the end of the frame. It is further noted that high performance longwave infrared imaging systems require large well depths to improve signal-to-noise ratio due to high background emission, which further encourages the use of in-pixel digital readouts.
While the use of split bit readouts in these and other applications is beneficial, such use is hampered where output data is not usable due to misalignment of the least significant counter bit (i.e., the LSB of the M most significant bits) and most significant residual bit (i.e. the MSB of the N least significant bits).